Home Forums Hardware discussions Are LAN0 and LAN1 bridged in hardware? Reply To: Are LAN0 and LAN1 bridged in hardware?


@barryf Thank you for doing the hard work; in addition you’re informing us where the .dtb files should go. Excellent work. 🙂

the “port-mask” under “mvswitch” is a binary bitmap of ports that should be enabled; a one means it’s enabled, a zero means it’s disabled.
The Topaz-switch has a total of 4 ports. According to Peter’s suggestion of setting port-mask to 0x03 in order to enable LAN0 and LAN1, but disable WAN, I believe that the port named ‘WAN’ is bit 2, then LAN0 would likely be bit 0 and LAN1 would likely be bit 1.

-But I do not think that bit 3 is the connection between the Topaz-switch and the CPU. I do believe, though, that it’s the unconnected port on the Topaz-switch.
My guess why this port has not been connected, is that the Topaz-switch is connected via a 2.5Gbit SerDes; that means we’d need 3 ports in order to saturate that 2.5Gbits; adding an extra port would still only give us a maximum of 2.5Gbit.

I do find it a little strange that the flash-interface is defined at the bottom of the .dtb file. If this file is loaded by uboot, which resides in flash; how does uboot know how to load it, because the file system would need to know the flash interface before the file can be loaded, right ? 🙂

… Hmm … Maybe uboot does not reside in SPI-flash, maybe SPI-flash only contains a bootloader, which loads uboot from eMMC/NAND/SATA/USB/SD …

… Did you mount /boot from SPI-flash or from eMMC/NAND ?

Note: I would have wished for the second SerDes being routed to a 1GbE port or another Topaz switch (or some optional footprints on the PCB) – I don’t know the details why this wasn’t done; it could be due to a pin/mux conflict.

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