I got the mPCIe slot working now. I had to apply this patch to the kernel:
--- drivers/pci/host/pci-aardvark.c 2018-03-02 21:59:56.553041000 +0100
+++ drivers/pci/host/pci-aardvark.c 2018-03-02 22:00:12.083041000 +0100
@@ -307,10 +307,10 @@
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
- /* Set GEN2 */
+ /* Set GEN1 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~PCIE_GEN_SEL_MSK;
- reg |= SPEED_GEN_2;
+ reg |= SPEED_GEN_1;
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
/* Set lane X1 */
Why on earth is this not done by Marvell? I had to do the same for OpenWRT.
